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High Efficiency Synchronous, Step Down Controller
POWER MANAGEMENT Description
The SC4602A/B is a voltage mode step down (buck) regulator controller that provides accurate high efficiency power conversion from an input supply range of 2.75V to 5.5V. A high level of integration reduces external component count and makes it suitable for low voltage applications where cost, size and efficiency are critical. The SC4602A/B drives external complementary power MOSFETs; P-channel on the high side and N-channel on the low side. The use of high side P-channel MOSFET eliminates the need for an external charge pump and simplifies the high side gate driver. Non-overlap protection is provided for the gate drive signals to prevent shoot through of the MOSFET pair. Voltage drop across the Pchannel MOSFET during its conduction is sensed for lossless short circuit current limiting. A low power sleep mode can be achieved by forcing the SYNC/SLEEP pin below 0.8V. A synchronous mode of operation is activated as the SYNC/SLEEP pin is driven by an external clock. The quiescent supply current in sleep mode is typically lower than 10A. A soft start (2.4ms for the SC4602A and 1.2ms for the SC4602B) is internally provided to prevent output voltage overshoot during startup. A 100% maximum duty cycle allows the SC4602A/B to operate as a low dropout regulator in the event of a low battery condition. The SC4602A/B has fixed switching frequency (300KHz for the SC4602A and 550KHz for the SC4602B). The SC4602A/B is an ideal choice for 3.3V, 5V or other low input supply sytems. It's available in a 8 pin MSOP package.
SC4602A/B
Features
BICMOS Voltage mode PWM controller 2.75V to 5.5V Input voltage range Output voltages as low as 0.8V +/-1% Reference accuracy Sleep Mode (Icc = 10A typ) Lossless short circuit current limiting Combination pulse by pulse & hiccup mode current limit High efficiency synchronous switching Up to 100% Duty cycle range Synchronization to external clock 8-Pin MSOP surface mount package. Lead-free package available, fully WEEE and RoHS compliant
Applications
Distributed power system RF power supply Local microprocessor core power supplies DSP and I/O power supplies Battery powered applications Servers and workstations
Typical Application Circuit
R15 1 M1 C10 22u
Vin = 2.75V ~ 5.5V
C11 22u C12 22u C13 22u
U1 1 C3 4.7u 2 3 4 C1 470p C2 6.8n R1 5.11k VCC PDRV 8 7 6 5
R6 1.0 L1 1.6u M2 R5 1.0 C7 150u C4 22u C9 3.3n R8 169 R7 4.64k
SY NC/SLEEP NDRV COMP VSENSE GND PHASE
Vo = 1.5V (as low as 0.8V )/6A
SC4602B
* External components can be modified to provide a VOUT as low as 0.8V.
Revision: January 20, 2006 1
R9 5.36k
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SC4602A/B
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Supply Voltage (VCC) Output Drivers (PDRV, NDRV) Currents Continuous Inputs (VSENSE, COMP, SYNC/SLEEP, FS, ISET) Phase Phase Pulse tpulse < 50ns Operating Ambient Temperature Range Storage Temperature Range Maximum Junction Temperature Thermal Impedance Junction to Case Thermal Impedance Junction to Ambient Lead Temperature (Soldering) 10 Sec. ESD Rating (Human Body Model)
Symbol
Maximum 7 0.25 -0.3 to 7 -0.3 to 7 -2 to 7
Units V A V V V C C C C/W C/W C kV
TA TSTG TJ J C J A TLEAD ESD
-40 to +85 -65 to +150 +150 41.9 113.1 +300 2
All voltages with respect to GND. Currents are positive into, negative out of the specified terminal.
Electrical Characteristics
Unless otherwise specified, VCC = 3.3V, TA = -40oC to 85oC, TA = TJ.
Parameter Overall Supply Voltage Supply Current, Sleep Supply Current, Operating VCC Turn-on Threshold VCC Turn-off Hysteresis Error Amplifier Internal Reference
Test Conditions
Min
Typ
Max
Unit
2.75 VSYNC/SLEEP = 0V 10 1.5 2.55 150
5.5 15 3 2.75
V A mA V mV
TA = 25C VCC = 2.75V to 5.5V, TA = 25C TA = -40oC to 85oC
0.792 0.788 0.784
0.8 0.8 0.8 25
0.808 0.812 0.816 nA dB MHz V/s
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V
VSENSE Bias Current Open Loop Gain
(1) (1)
VCOMP = 0.4V to 1.8V
70
80 4 2
Unity Gain Bandwidth Slew Rate
(1)
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SC4602A/B
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless otherwise specified, VCC = 3.3V, TA = -40oC to 85oC, TA = TJ.
Parameter Error Amplifier (Cont.) VCOMP High VCOMP Low Oscillator Initial Accuracy (SC4602A) Initial Accuracy (SC4602B) SYNC/SLEEP Low Threshold SYNC/SLEEP High Threshold Ramp Peak to Valley (1) Ramp Peak Voltage Ramp Valley Voltage
(1) (1)
Test Conditions
Min
Typ
Max
Unit
ICOMP = -2mA ICOMP = 2mA
2.8
3.1 0.15 0.3
V V
TA = 25C, VSYNC = HIGH TA = 25C, VSYNC = HIGH
260 480
300 550
340 620 0.8
kHz kHz V V
2.0 1.3 1.5 1.85 0.3 0.35 1.7 1.9
V V V
Sleep, Soft Start, Current Limit Sleep Input Bias Current Soft Start Time
(1)
VSYNC/SLEEP = 0V S C 4602A S C 4602B
-1 2.4 1.2 -300 0.4 150
A ms
Current Limit Threshold
(2)
Reference to VCC, TJ = 25C Temperature coefficient
mV %/C ns
Current Limit Blank Time
(1)
N-Channel and P-Channel Driver Outputs Pull Up Resistance (PDRV) (2) Pull Down Resistance (PDRV) (2) Pull Up Resistance (NDRV) (2) Pull Down Resistance (NDRV) (2) PDRV Output Rise Time PDRV Output Fall Time
(1) (1)
Vcc = 3.3V, IOUT = -100mA (source) Vcc = 3.3V, IOUT = 50mA (sink) Vcc = 3.3V, IOUT = -100mA (source) Vcc = 3.3V, IOUT = 100mA (sink) Vgs = 3.3V, COUT = 1.0nF Vgs = 3.3V, COUT = 1.0nF 9 12
3 3 3 3
ohms ohms ohms ohms ns ns
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SC4602A/B
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless otherwise specified, VCC = 3.3V, TA = -40oC to 85oC, TA = TJ.
Parameter
Test Conditions
Min
Typ
Max
Unit
N-channel and P-Channel Driver Outputs (Cont.) NDRV Output Rise Time NDRV Output Fall Time
(1) (1)
Vgs = 3.3V, COUT = 1.0nF Vgs = 3.3V, COUT = 1.0nF
15 15 adaptive 50
ns ns
Deadtime Delay (PDRV high to NDRV high) (1) Deadtime Delay (NDRV low to PDRV low) (1)
ns
Notes: (1) Guaranteed by design. (2) Guaranteed by characterization. (3) Dead time delay from PDRV high to NDRV high is adaptive. As the phase node voltage drops below 600mV due to PDRV high, NDRV will start to turn high.
Marking Information
yyww = Date Code (Example: 0012) xxxxxxxx = Semtech Lot No. (Example: E901 01-1)
yyww = Date Code (Example: 0012) xxxxxxxx = Semtech Lot No. (Example: E901 01-1)
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SC4602A/B
POWER MANAGEMENT Pin Configuration
Top View
Ordering Information
Part Number(1) SC4602AIMSTR SC4602AIMSTRT(2) SC4602BIMSTR SC4602BIMSTRT(2) kH z 300 Device MSOP-8
550
MSOP-8
(8 Pin MSOP)
S C 4602A E V B S C 4602B E V B
Evaluation Board
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant.
Pin Descriptions
VCC: Positive supply rail for the IC. Bypass this pin to GND with a 0.1 to 4.7F low ESL/ESR ceramic capacitor. GND: All voltages are measured with respect to this pin. All bypass and timing capacitors connected to GND should have leads as short and direct as possible. SYNC/SLEEP: The oscillator of SC4602A and SC4602B are set to 300kHz and 550kHz respectively when SYNC/ SLEEP is pulled and held above 2V. Synchronous mode operation is activated as the SYNC/SLEEP is driven by an external clock. The oscillator and PWM are designed to provide practical operation to 450kHz for SC4602A and to 700kHz for SC4602B when synchronized. Sleep mode is invoked if SYNC/SLEEP is pulled and held below 0.8V which can be accomplished by an external gate or transistor. Sleepmode supply current is 10A typical. VSENSE: This pin is the inverting input of the voltage amplifier and serves as the output voltage feedback point for the Buck converter. It senses the output voltage through an external divider. COMP: This is the output of the voltage amplifier. The voltage at this output is inverted internally and connected to the non-inverting input of the PWM comparator. A leadlag network around the voltage amplifier compensates for the two pole LC filter characteristic inherent to voltage mode control and is required in order to optimize the dynamic performance of the voltage mode control loop.
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PHASE: This input is connected to the junction between the two external power MOSFET transistors. The voltage drop across the upper P-channel device is monitored by PHASE during conduction and forms the current limit comparator. Logic sets the PWM latch and terminates the output pulse. The controller stops switching and goes through a soft start sequence once the converter output voltage drops below 68.75% its nominal voltage. This prevents excess power dissipation in the PMOSFET during a short circuit. The reverse current comparator senses the drop across the lower N-channel MOSFET during its conduction and disables the drive signal if a small positive voltage is present. To disable the overcurrent comparator, connect PHASE to VCC. PDRV, NDRV: The PWM circuitry provides complementary drive signals to the output stages. Cross conduction of the external MOSFETS is prevented by monitoring the voltage on the P-channel and N-channel driver pins in conjunction with a time delay optimized for FET turnoff characteristics.
SC4602A/B
POWER MANAGEMENT Block Diagram
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SC4602A/B
POWER MANAGEMENT Typical Characteristic (Cont.)
Current Limit Threshold Voltage vs Input Voltage
Current Limit Threshold Voltage (mV)
TA = 25C
Current Limit Threshold Voltage vs Temperature
Current Limit Threshold Voltage (mV)
-280.00 -285.00 -290.00 -295.00 -300.00 -305.00 -310.00
-200.00 -250.00 -300.00 -350.00
Vcc = 3.3V
-400.00 -40 -20 0 20 40 60 80
Temperature (C)
2.5
3
3.5
4
Vcc (V)
4.5
5
5.5
Sc4602A Oscillator Internal Accuracy vs Input Voltage
Internal Accuracy (kHz)
Sc4602A Oscillator Internal Accuracy vs Temperature
300.000 295.000 290.000 285.000 280.000 275.000 270.000 -40
Vcc = 3.3V
Internal Accuracy (kHz)
290.000 285.000 280.000 275.000 2.5
TA = 25C
3
3.5
4
Vcc (V)
4.5
5
5.5
-20
0
20
40
60
80
Temperature (C)
Sc4602A Sense Voltage vs Input Voltage
803.400 803.200 803.000 802.800 802.600 802.400 802.200 802.000 2.5
Sense Voltage (mV)
TA = 25C
Sc4602A Sense Voltage vs Temperature
Sense Voltage (mV)
803.000 802.000 801.000 800.000 799.000 798.000
Vcc = 3.3V
3
3.5
4
Vcc (V)
4.5
5
5.5
-40
-20
0
20
40
60
80
Temperature (C)
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SC4602A/B
POWER MANAGEMENT Typical Characteristic (Cont.)
Sc4602B Oscillator Internal Accuracy vs Input Voltage
560.000 555.000 550.000 545.000 540.000 535.000 530.000 525.000 570.000 560.000 550.000 540.000 530.000 520.000 -40
Sc4602B Oscillator Internal Accuracy vs Temperature
Internal Accuracy (kHz)
Vcc = 3.3V
Internal Accuracy (kHz)
TA = 25C
2.5
3
3.5
4
Vcc (V)
4.5
5
5.5
-20
0
20
40
60
80
Temperature (C)
Sc4602B Sense Voltage vs Input Voltage
801.000 800.800 800.600 800.400 800.200 800.000 799.800 799.600 2.5
Sense Voltage (mV)
TA = 25C
Sc4602B Sense Voltage vs Temperature
Sense Voltage (mV)
800.500 800.000 799.500 799.000 798.500
Vcc = 3.3V
3
3.5
4
Vcc (V)
4.5
5
5.5
-40
-20
0
20
40
60
80
Temperature (C)
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SC4602A/B
POWER MANAGEMENT Applications Information
Enable Pulling and holding the SYNC/SLEEP pin below 0.8V initializes the SLEEP mode of the SC4602A/B with its typical SLEEP mode supply current of 10uA. During the SLEEP mode, the high side and low side MOSFETs are turned off and the internal soft start voltage is held low. Oscillator The SC4602A/B is a constant frequency, voltage mode, and synchronous step down controller ideal for low voltage, high efficiency, precisely regulated output DC/DC converters. Its internal free running oscillator sets the PWM frequency at 300kHz for the SC4602A and 550kHz for the SC4602B without any external components to set the frequency. A 100% maximum duty cycle allows the SC4602A/B to operate as a low dropout regulator in the event of a low battery condition. An external clock connected to SYNC/SLEEP activates its synchronous mode and the frequency of the clock can be up to 450kHz for the SC4602A and 700kH for the SC4602B. UVLO When the SYNC/SLEEP pin is pulled and held above 2V, the voltage on the Vcc pin determines the operation of the SC4602A/B. As Vcc increases during start up, the UVLO block senses Vcc and keeps the high side and low side MOSFETs off and the internal soft start voltage low until Vcc reaches 2.75V. If no faults are present, the SC4602A/B will initiate a soft start when Vcc exceeds 2.75V. A hysteresis (150mV) in the UVLO comparator provides noise immunity during its start up. Soft Start The soft start function is required for step down controllers to prevent excess inrush current through the DC bus during start up. Generally this can be done by sourcing a controlled current into a timing capacitor and then using the voltage across this capacitor to slowly ramp up the error amp reference. The closed loop creates narrow width driver pulses while the output voltage is low and allows these pulses to increase to their steady state duty cycle as the output voltage reaches its regulated value. With this, the inrush current from the input side is controlled. The duration of the soft start in the SC4602A/B is controlled by an internal timing circuit which is used
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during start up and over current to set the hiccup time. The soft start time can be calculated by:
TSOFT _ START = 720 fs
As can be seen here, the soft start time is switching frequency dependant. For example, if fs = 300kHz, TSOFT_START = 720/300k = 2.4ms. But if fs = 600kHz, TSOFT_START = 720/600k = 1.2ms. The SC4602A/B implements its soft start by ramping up the error amplifier reference voltage providing a controlled slew rate of the output voltage, then preventing overshoot and limiting inrush current during its start up. Over Current Protection Over current protection for the SC4602A/B is implemented by detecting the voltage drop of the high side PMOSFET during conduction, also known as high side RDS(ON) detection. This loss-less detection eliminates the sense resistor and its loss. The overall efficiency is improved, and the number of components and cost of the converter are reduced. RDS(ON) sensing is by default inaccurate and is mainly used to protect the power supply during a fault case. The over current trigger point will vary from unit to unit as the RDS(ON) of P-MOSFET varies. Even for the same unit, the over current trigger point will vary as the junction temperature of P-MOSFET varies. The SC4602A/B provides a built-in 300mV voltage source. The over current trigger point can be determined based on the internal 300mV voltage source and the RDS(ON) of P-MOSFET as follows:
Itrigger = 300mV RDS( ON)
Kelvin sensing connections should be used at the drain and source of P-MOSFET. The RDS(ON) sensing used in the SC4602A/B has an additional feature that enhances the performance of the over current protection. Because the RDS(ON) has a positive temperature coefficient, the 300mV voltage source has a positive coefficient of about 0.4%/C providing first order correction for current sensing vs temperature. This compensation depends on the high amount of thermal transferring that typically exists between the high side PMOSFET and the SC4602A/B due to the compact layout of the power supply.
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SC4602A/B
POWER MANAGEMENT Applications Information (Cont.)
When the converter detects an over current condition (I > IMAX) as shown in Figure 1, the first action the SC4602A/ B takes is to enter cycle by cycle protection mode (Point B to Point C), which responds to minor over current cases. Then the output voltage is monitored. If the over current and low output voltage (set at 68.75% of nominal output voltage) occur at the same time, the Hiccup mode operation (Point C to Point D) of the SC4602A/B is invoked and the internal soft start capacitor is discharged. This is like a typical soft start cycle.
tween two MOSFETs and minimizes the conduction loss in the bottom diode for high efficiency applications.
PMOSFET Gate Drive NMOSFET Gate Drive
Phase node
Ground
td1
td2
A
VO - nom
Figure 2. Timing Waveforms for Gate Drives and Phase Node
B
Inductor Selection
0.6875 VO - nom
VO
0.125 VO - nom
D IMA IO
C
Figure 1. Over current protection characteristic of SC4602A/B Power MOSFET Drivers The SC4602A/B has two drivers for external complementary power MOSFETs. The driver block consists of one high side P-MOSFET, 4 driver, PDRV, and one low side 5, N-MOSFET driver, NDRV, which are optimized for driving external power MOSFETs in a synchronous buck converter. The output drivers also have gate drive non-overlap mechanism that gives a dead time between PDRV and NDRV transitions to avoid potential shoot through problems in the external MOSFETs. By using the proper design and the appropriate MOSFETs, a 6A converter can be achieved. As shown in Figure 2, td1, the delay from the P-MOSFET off to the N-MOSFET on is adaptive by detecting the voltage of the phase node. td2, the delay from the N-MOSFET off to the P-MOSFET on is fixed, is 100ns for the SC4602A/B. This control scheme guarantees avoiding the cross conduction or shoot through be-
The factors for selecting the inductor include its cost, efficiency, size and EMI. For a typical SC4602A/B application, the inductor selection is mainly based on its value, saturation current and DC resistance. Increasing the inductor value will decrease the ripple level of the output voltage while the output transient response will be degraded. Low value inductors offer small size and fast transient responses while they cause large ripple currents, poor efficiencies and more output capacitance to smooth out the large ripple currents. The inductor should be able to handle the peak current without saturating and its copper resistance in the winding should be as low as possible to minimize its resistive power loss. A good tradeoff among its size, loss and cost is to set the inductor ripple current to be within 15% to 30% of the maximum output current. The inductor value can be determined according to its operating point and the switching frequency as follows:
L= VO ( VI - VO ) VI fs I IOMAX
Where: fs = switching frequency and I = ratio of the peak to peak inductor current to the maximum output load current. The peak to peak inductor current is:
IP -P = I * IOMAX
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SC4602A/B
POWER MANAGEMENT Applications Information (Cont.)
After the required inductor value is selected, the proper selection of the core material is based on the peak inductor current and efficiency requirements. The core must be able to handle the peak inductor current IPEAK without saturation and produce low core loss during the high frequency operation.
IPEAK = IOMAX + Ip -p 2
Input Capacitor Selection The input capacitor selection is based on its ripple current level, required capacitance and voltage rating. This capacitor must be able to provide the ripple current by the switching actions. For the continuous conduction mode, the RMS value of the input capacitor can be calculated from:
ICIN (RMS ) = IOMAX VO ( VI - VO ) V 2I
The power loss for the inductor includes its core loss and copper loss. If possible, the winding resistance should be minimized to reduce inductor's copper loss. The core loss can be found in the manufacturer's datasheet. The inductor' copper loss can be estimated as follows:
PCOPPER = I2LRMS R WINDING
This current gives the capacitor's power loss as follows:
PCIN = I2 CIN(RMS ) R CIN(ESR )
Where: ILRMS is the RMS current in the inductor. This current can be calculated as follows:
ILRMS = IOMAX 1 + 1 I2 3
Output Capacitor Selection Basically there are two major factors to consider in selecting the type and quantity of the output capacitors. The first one is the required ESR (Equivalent Series Resistance) which should be low enough to reduce the voltage deviation from its nominal one during its load changes. The second one is the required capacitance, which should be high enough to hold up the output voltage. Before the SC4602A/B regulates the inductor current to a new value during a load transient, the output capacitor delivers all the additional current needed by the load. The ESR and ESL of the output capacitor, the loop parasitic inductance between the output capacitor and the load combined with inductor ripple current are all major contributors to the output voltage ripple. Surface mount speciality polymer aluminum electrolytic chip capacitors in UE series from Panasonic provide low ESR and reduce the total capacitance required for a fast transient response. POSCAP from Sanyo is a solid electrolytic chip capacitor which has a low ESR and good performance for high frequency with a low profile and high capacitance. Above mentioned capacitors are recommended to use in SC4602A/B applications.
This capacitor's RMS loss can be a significant part of the total loss in the converter and reduce the overall converter efficiency. The input ripple voltage mainly depends on the input capacitor's ESR and its capacitance for a given load, input voltage and output voltage. Assuming that the input current of the converter is constant, the required input capacitance for a given voltage ripple can be calculated by:
CIN = IOMAX D (1 - D) fs ( VI - IOMAX R CIN(ESR ) )
Where: D = VO/VI , duty ratio and DVI = the given input voltage ripple. Because the input capacitor is exposed to the large surge current, attention is needed for the input capacitor. If tantalum capacitors are used at the input side of the converter, one needs to ensure that the RMS and surge ratings are not exceeded. For generic tantalum capacitors, it is wise to derate their voltage ratings at a ratio of 2 to protect these input capacitors. Power Mosfet Selection The SC4602A/B can drive a P-MOSFET at the high side and an N-MOSFET synchronous rectifier at the low side. The use of the high side P-MOSFET eliminates the need for an external charge pump and simplifies the high side gate driver circuit.
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SC4602A/B
POWER MANAGEMENT Applications Information (Cont.)
For the top MOSFET, its total power loss includes its conduction loss, switching loss, gate charge loss, output capacitance loss and the loss related to the reverse recovery of the bottom diode, shown as follows:
PTOP _ TOTAL = I2 TOP _ RMS R TOP _ ON + ITOP _ PEAK VI fs (Q GD + Q GS2 ) + Q GT VGATE fs + (Q OSS + Qrr ) VI fs VGATE RG
Loop Compensation Design For a DC/DC converter, it is usually required that the converter has a loop gain of a high cross-over frequency for fast load response, high DC and low frequency gain for low steady state error, and enough phase margin for its operating stability. Often one can not have all these properties at the same time. The purpose of the loop compensation is to arrange the poles and zeros of the compensation network to meet the requirements for a specific application. The SC4602A/B has an internal error amplifier and requires the compensation network to connect among the COMP pin and VSENSE pin, GND, and the output as shown in Figure 3. The compensation network includes C1, C2, R1, R7, R8 and C9. R9 is used to program the output voltage according to:
VO = 0.8 (1 + R7 ) R9
Where: RG = gate drive resistor, QGD = the gate to drain charge of the top MOSFET, QGS2 = the gate to source charge of the top MOSFET, QGT = the total gate charge of the top MOSFET, QOSS = the output charge of the top MOSFET and Qrr = the reverse recovery charge of the bottom diode. For the top MOSFET, it experiences high current and high voltage overlap during each on/off transition. But for the bottom MOSFET, its switching voltage is the bottom diode's forward drop during its on/off transition. So the switching loss for the bottom MOSFET is negligible. Its total power loss can be determined by:
PBOT _ TOTAL = I2 BOT _ RMS R BOT _ ON + Q GB VGATE fs + ID _ AVG VF
VCC
PDRV
SYNC/SLEEP NDRV COMP GND PHASE C9 R7 C4 L1
Vo
Where: QGB = the total gate charge of the bottom MOSFET and VF = the forward voltage drop of the bottom diode. For a low voltage and high output current application such as the 3.3V/1.5V@6A case, the conduction loss is often dominant and selecting low RDS(ON) MOSFETs will noticeably improve the efficiency of the converter even though they give higher switching losses. The gate charge loss portion of the top/bottom MOSFET's total power loss is derived from the SC4602A/B. This gate charge loss is based on certain operating conditions (fs, VGATE, and IO). The thermal estimations have to be done for both MOSFETs to make sure that their junction temperatures do not exceed their thermal ratings according to their total power losses PTOTAL, ambient temperature Ta and their thermal resistances Rja as follows:
Tj(max) < Ta +
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C2
VSENSE
SC4602A/B
C1
R1
R8
R9
Figure 3. Compensation network provides 3 poles and 2 zeros. For voltage mode step down applications as shown in Figure 3, the power stage transfer function is:
1+ G VD (s) = VI s 1 RC C4
1+ s
L1 + s 2L 1C 4 R
PTOTAL R ja
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SC4602A/B
POWER MANAGEMENT Applications Information (Cont.)
Where: R = load resistance and RC = C4's ESR. The compensation network will have the characteristic as follows:
s s 1+ Z1 Z 2 GCOMP (s) = I s 1+ s 1+ s P1 P 2 1+
The design guidelines for the SC4602A/B applications are as following: 1. Set the loop gain crossover corner frequency C for given switching corner frequency S =2pfs, 2. Place an integrator at the origin to increase DC and low frequency gains, 3. Select Z1 and Z2 such that they are placed near O to damp the peaking and the loop gain has a -20dB/dec rate to go across the 0dB line for obtaining a wide bandwidth, 4. Cancel the zero from C4's ESR by a compensator pole P1 (P1 = ESR = 1/( RCC4)), 5. Place a high frequency compensator pole p2 (p2 = pfs) to get the maximum attenuation of the switching ripple and high frequency noise with the adequate phase lag at C. The compensated loop gain will be as given in Figure 4:
Where:
I = 1 R 7 ( C1 + C 2 ) 1 R1 C 2
Z1 = Z 2 =
1 (R 7 + R 8 ) C 9 C1 + C 2 R 1 C1 C 2 1 = R 8 C9
P1 = P 2
T Z1 o Z2 Gd c p1 p2 Power stage GVD(s) ESR -40dB/dec 0dB Loop gain T(s) -20dB/dec
After the compensation, the converter will have the following loop gain:
T(s) = GPWM GCOMP (s) G VD (s) s 1+ 1 s 1 s 1+ I VI 1 + RC C4 Z1 Z 2 VM = s L s s 1+ 1 + s 1 + s2L1C 4 1+ R P1 P 2
Figure 4. Asymptotic diagrams of power stage and its loop gain
Where: GPWM = PWM gain and VM = 1.5V, ramp peak to valley voltage of SC4602A/B.
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SC4602A/B
POWER MANAGEMENT Applications Information (Cont.)
Layout Guideline In order to achieve optimal electrical, thermal and noise performance for high frequency converters, special attention must be paid to the PCB layouts. The goal of layout optimization is to identify the high di/dt loops and minimize them. The following guideline should be used to ensure proper functions of the converters. 1. A ground plane is recommended to minimize noises and copper losses, and maximize heat dissipation. 2. Start the PCB layout by placing the power components first. Arrange the power circuit to achieve a clean power flow route. Put all the connections on one side of the PCB with wide copper filled areas if possible. 3. The Vcc bypass capacitor should be placed next to the Vcc and GND pins. 4. The trace connecting the feedback resistors to the output should be short, direct and far away from the noise sources such as the phase node and switching components. 5. Minimize the traces between PDRV/NDRV and the gates of the MOSFETs to reduce their impedance to drive the MOSFETs. 6. Minimize the loop including input capacitors, top/bottom MOSFETs. This loop passes high di/dt current. Make sure the trace width is wide enough to reduce copper losses in this loop. 7. The PHASE connection to P-MOSFET for current sensing must use Kelvin connection. 8. Maximize the trace width of the loop connecting the inductor, bottom MOSFET and the output capacitors. 9. Connect the ground of the feedback divider and the compensation components directly to the GND pin of the SC4602A/B by using a separate ground trace. Then connect this pin to the ground of the output capacitor as close as possible.
A Design Example: 3.3V to1.5V @6A application with SC4602B (NH020 footprint)
GND
1 2 3
R15 1 M1 C10 22u U1 1 C3 4.7u R2 3.32K 2 3 4 C1 470p C2 6.8n R1 5.11k 1.0 VCC PDRV 8 7 6 5 R5 C11 22u
Vin = 3.3V
C12 22u C13 22u ON/OFF
4 5 6 J1
R6 1.0 M2 L1 1.6u C7 150u C4 22u C9 3.3n R8 169 R10 100 TRIM R7 4.64k
SY NC/SLEEP NDRV COMP VSENSE GND PHASE
Vo = 1.5V/6A
1 2 3 4 5 J2
SC4602B
R11 100 ON/OFF
R9 5.36k
Figure 5. Schematic for 3.3V/1.5V@6A with SC4602B application
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SC4602A/B
POWER MANAGEMENT Bill of Materials - 3.3V to 1.5V @ 6A
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Qty 1 1 1 5 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 C1 C2 C3 C4, C10, C11, C12, C13 C7 C9 J1 J2 L1 M1 M1 R1 R2 R15 R5, R6 R7 R8 R9 R10, R11 U1 Reference 470pF 6.8nF 4.7uF 22uF SP capacitor, 150uF, 15 mohm, 6.3V 3.3nF CON6 CON5 SMT power inductor, 1.6uH +/- 30%, 12.2A, 3.3 mohm max FDS 6375, SO-8, Fairchild FDS 6680A, SO-8, Fairchild 5.11k 3.32k 1 1.0 4.64k 169 5.36k 100 S C 4602B Semtech P/N: SC4602BIMSTR Panasonic. P/N: ETQP6F1R6S SO-8 MOSFET P SO-8 MOSFET N 0805, ceramic TDK P/N: C3225X5R0J226M Panasonic Value Part No./Manufacturer
Key components: U1: SC4602B, Semtech M1: FDS 6375, SO-8, Fairchild M2: FDS 6680A, SO-8, Fairchild C7: SP capacitor, 150uF, 15 mohm, 6.3V, Panasonic L1: SMT power inductor, 1.6uH +/- 30%, 12.2A, 3.3 mohn max. ETQP6F1R6S Panasonic. Unless specified, all resistors and capacitors are in SMD 0603 package. Resistors are +/-1% and all capacitors are +/-20%
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SC4602A/B
POWER MANAGEMENT PCB Layout - 3.3V to 1.5V @ 6A
PCB layout information for 3.3V to1.5V @6A with SC4602B application (NH020 footprint) Top
Bottom
Top
Bottom
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SC4602A/B
POWER MANAGEMENT Typical Characteristic
Over current protection characteristic of SC4602B for 3.3V to1.5V @6A application: The over current protection curve below is obtained by applying a gradually increased load while the load current and the output voltage are monitored and measured. When the load current is increased from 0 to 9A (over current trigger point), the output voltage is 1.5V, corresponding from Point A to Point B. As the load current increases further from 9A to 9.6A, the output voltage drops significantly from 1.5V (Point B) to 0.54V (Point C). Because an over current and a lower output voltage (0.54V<68.75%*1.5V=1.03V) are present at Point C, the SC4602B enters its HICCUP mode. Then the locus of the output current and the output voltage follows Line CD as shown in the curve. Due to the over current applied, the HICCUP protection will go back and forth on Line CD. This prevents excess power dissipation in the P-MOSFET during a short output conditio
Overcurrent protection
3 Output Voltage (V) 2.5 2 1.5 1 0.5 0 0 3 6 9 12 15 18 Output Current (A)
A
B C
D
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SC4602A/B
POWER MANAGEMENT Outline Drawing - MSOP-8
e/2 A N 2X E/2 PIN 1 INDICATOR ccc C 2X N/2 TIPS 12 e B E1 E D
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
DIMENSIONS MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX
.043 .000 .006 .030 .037 .009 .015 .009 .003 .114 .118 .122 .114 .118 .122 .193 BSC .026 BSC .016 .024 .032 (.037) 8 0 8 .004 .005 .010 1.10 0.00 0.15 0.75 0.95 0.22 0.38 0.08 0.23 2.90 3.00 3.10 2.90 3.00 3.10 4.90 BSC 0.65 BSC 0.40 0.60 0.80 (.95) 8 0 8 0.10 0.13 0.25
aaa C SEATING PLANE
D A2 A GAGE PLANE 0.25
H c
C
A1 bxN bbb C A-B D
L (L1) DETAIL
01
A
SIDE VIEW
NOTES: 1.
SEE DETAIL
A
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-187, VARIATION AA.
Land Pattern - MSOP-8
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.161) .098 .026 .016 .063 .224 (4.10) 2.50 0.65 0.40 1.60 5.70
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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